SN74ABT841A - 10-Bit Bus-Interface D-Type Latches With 3-State Outputs

The SN54ABT841 and SN74ABT841A 10-bit latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The ten transparent D-type latches provide true data at their outputs.

A buffered output-enable (OE\) input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT841 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT841A is characterized for operation from -40°C to 85°C.

Products containing the "SN74ABT841A" keyword are: SN74ABT841ADBR , SN74ABT841ADBR , SN74ABT841ADBR AB841A , SN74ABT841ADBRE4 , SN74ABT841ADBRE4 , SN74ABT841ADBRG4 , SN74ABT841ADW , SN74ABT841ADW , SN74ABT841ADWG4 , SN74ABT841ADWG4 , SN74ABT841ADWR , SN74ABT841ADWR , SN74ABT841ADWRE4 , SN74ABT841ADWRE4 , SN74ABT841ANSR , SN74ABT841ANT , SN74ABT841ANT , SN74ABT841APW , SN74ABT841APW , SN74ABT841APWR

• State-of-the-Art EPIC-II B^TM BiCMOS Design Significantly Reduces Power Dissipation
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
• High-Impedance State During Power Up and Power Down
• High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs

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