SN74ABT377A - Octal Edge-Triggered D-Type Flip-Flops With Clock Enable

These 8-bit positive-edge-triggered D-type flip-flops with a clock (CLK) input are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators.

Data (D) input information that meets the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the common clock-enable () input is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the buffered clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at .

The SN54ABT377 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT377A is characterized for operation from -40°C to 85°C.

 

 

Products containing the "SN74ABT377A" keyword are: SN74ABT377ADBR , SN74ABT377ADBR , SN74ABT377ADBR AB377A , SN74ABT377ADBRG4 , SN74ABT377ADW , SN74ABT377ADW , SN74ABT377ADWE4 , SN74ABT377ADWE4 , SN74ABT377ADWG4 , SN74ABT377ADWG4 , SN74ABT377ADWR , SN74ABT377ADWR , SN74ABT377ADWRG4 , SN74ABT377AN , SN74ABT377AN , SN74ABT377ANS , SN74ABT377ANSR , SN74ABT377ANSR , SN74ABT377ANSRG4 , SN74ABT377APW

• State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
• High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package

 

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