CY74FCT273T - Octal D-Type Flip-Flops with Clear

The \x92FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR\) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flop\x92s Q output. All outputs are forced low by a low logic level on the MR\ input.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Products containing the "CY74FCT273T" keyword are: CY74FCT273TQC , CY74FCT273TQCT , CY74FCT273TQCT , CY74FCT273TQCTG4 , CY74FCT273TSOC , CY74FCT273TSOC , CY74FCT273TSOCE4 , CY74FCT273TSOCG4 , CY74FCT273TSOCT , CY74FCT273TSOCT , CY74FCT273TSOCTE4 , CY74FCT273TSOCTG4

• Function, Pinout, and Drive Compatible With FCT and F Logic
• Reduced V_OH (Typically = 3.3 V) Versions of Equivalent FCT Functions
• Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
• I_off Supports Partial-Power-Down Mode Operation
• Matched Rise and Fall Times
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)
• Fully Compatible With TTL Input and Output Logic Levels
• CY54FCT273T
  • 32-mA Output Sink Current
  • 12-mA Output Source Current
• CY74FCT273T
  • 64-mA Output Sink Current
  • 32-mA Output Source Current