SN74LV573A - Octal Transparent D-Type Latches With 3-State Outputs

The ’LV573A devices are octal transparent D-type latches designed for 2-V to 5.5-V V_CC operation.

These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

Products containing the "SN74LV573A" keyword are: SN74LV573ADBR , SN74LV573ADBR , SN74LV573ADBR(LVC573) , SN74LV573ADBRG4 , SN74LV573ADBRG4 , SN74LV573ADGVR , SN74LV573ADGVR , SN74LV573ADW , SN74LV573ADW , SN74LV573ADWG4 , SN74LV573ADWR , SN74LV573ADWR , SN74LV573ADWRG4 , SN74LV573AGQNR , SN74LV573AGQNR , SN74LV573ANSR , SN74LV573ANSR , SN74LV573ANSRG4 , SN74LV573APW , SN74LV573APW

• 2-V to 5.5-V V_CC Operation
• Max t_pd of 8 ns at 5 V
• Typical V_OLP (Output Ground Bounce)
     <0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
     >2.3 V at V_CC = 3.3 V, T_A = 25°C
• Supports Mixed-Mode Voltage Operation on All Ports
• I_off Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)