SN74ABT533A - Octal Transparent D-Type Latches With 3-State Outputs

These octal transparent D-type latches with 3-state outputs are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

When the latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverse of the levels at the D inputs.

A buffered output-enable () input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

does not affect the internal operations of the latches. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT533 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT533A is characterized for operation from -40°C to 85°C.

 

Products containing the "SN74ABT533A" keyword are: SN74ABT533ADBR , SN74ABT533ADBR , SN74ABT533ADBR SSOP20 , SN74ABT533ADBRE4 , SN74ABT533ADBRE4 , SN74ABT533ADBRG4 , SN74ABT533ADW , SN74ABT533ADW , SN74ABT533ADWR , SN74ABT533ADWR , SN74ABT533ADWRE4 , SN74ABT533ADWRG4 , SN74ABT533AN , SN74ABT533AN , SN74ABT533ANSR , SN74ABT533ANSRE4 , SN74ABT533ANSRE4 , SN74ABT533APWE4 , SN74ABT533APWG4 , SN74ABT533APWR

• State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
• High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package

 

EPIC-IIB is a trademark of Texas Instruments Incorporated.