This 8-bit parallel-out serial shift register features AND-gated serial (A and B) inputs and an asynchronous clear (CLR\) input. The gated serial inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.
The SN74ALS164A is characterized for operation from 0°C to 70°C.
Products containing the "SN74ALS164A" keyword are: SN74ALS164AD , SN74ALS164AD , SN74ALS164ADG4 , SN74ALS164ADG4 , SN74ALS164ADR , SN74ALS164ADR , SN74ALS164ADRG4 , SN74ALS164AN , SN74ALS164AN , SN74ALS164AN-TI , SN74ALS164ANE4 , SN74ALS164ANR , SN74ALS164ANS , SN74ALS164ANS-TE2 , SN74ALS164ANSE4 , SN74ALS164ANSR , SN74ALS164ANSR , SN74ALS164ANSR SOP5.2| Status | ACTIVE |
| SubFamily | Shift register |
| Technology Family | ALS |
| VCC | 5.5 |
| Bits | 8 |
| Voltage | 5 |
| F @ nom voltage | 75 |
| ICC @ nom voltage | 24 |
| tpd @ Nom Voltage | 17 |
| 3-state output | No |
| Rating | Catalog |
| Operating temperature range | 0 to 70 |
| Package Group | PDIP|14 |
| Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
| Approx. price | 0.88 | 1ku |