SN74AC563 - Octal D-Type Transparent Latches With 3-State Outputs

The ’AC563 devices are octal D-type transparent latches with 3-state outputs. When the latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverse logic levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

(OE)\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Products containing the "SN74AC563" keyword are: SN74AC563DBR , SN74AC563DBR , SN74AC563DBRG4 , SN74AC563DW , SN74AC563DW , SN74AC563DWR , SN74AC563DWR , SN74AC563DWRE4 , SN74AC563DWRE4 , SN74AC563DWRG4 , SN74AC563DWRG4 , SN74AC563N , SN74AC563N , SN74AC563NS , SN74AC563NSE4 , SN74AC563NSR , SN74AC563NSRE4 , SN74AC563NSRG4 , SN74AC563PW , SN74AC563PW

• 2-V to 6-V V_CC Operation
• Inputs Accept Voltages to 6 V
• Max t_pd of 9 ns at 5 V
• 3-State Inverting Outputs Drive Bus Lines Directly
• Full Parallel Access for Loading
• Flow-Through Architecture to Optimize PCB Layout