SN74ABT162841 - 20-Bit Bus-Interface D-Type Latches With 3-State Outputs

These 20-bit transparent D-type latches feature noninverting 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The ’ABT162841 devices can be used as two 10-bit latches or one 20-bit latch. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (1OE\ or 2OE\) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

The outputs, which are designed to sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE\ shall be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

OE\ does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Products containing the "SN74ABT162841" keyword are: SN74ABT162841DGGR , SN74ABT162841DGGR , SN74ABT162841DL , SN74ABT162841DL , SN74ABT162841DLR , SN74ABT162841DLR

• Members of the Texas Instruments Widebus™ Family
• Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required
• Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 5 V, T_A = 25°C
• High-Impedance State During Power Up and Power Down
• I_off and Power-Up 3-State Support Hot Insertion
• Distributed V_CC and GND Pins Minimize High-Speed Switching Noise
• Flow-Through Architecture Optimizes PCB Layout
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17

Widebus is a trademark of Texas Instruments.