SN74AHCT16374 - 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs

The 'AHCT16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54AHCT16374 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AHCT16374 is characterized for operation from -40°C to 85°C.

Products containing the "SN74AHCT16374" keyword are: SN74AHCT16374DGGR , SN74AHCT16374DGGR , SN74AHCT16374DGGRG4 , SN74AHCT16374DGVR , SN74AHCT16374DGVR , SN74AHCT16374DL , SN74AHCT16374DL , SN74AHCT16374DLG4 , SN74AHCT16374DLG4 , SN74AHCT16374DLR , SN74AHCT16374DLR

• Members of the Texas Instruments Widebus^TM Family
• EPIC^TM (Enhanced-Performance Implanted CMOS) Process
• Inputs Are TTL-Voltage Compatible
• Distributed V_CC and GND Pins Minimize High-Speed Switching Noise
• Flow-Through Architecture Optimizes PCB Layout
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

EPIC and Widebus are trademarks of Texas Instruments Incorporated.