SN74AUC2G241 - Dual Buffer/Driver with 3-State Outputs

This dual buffer/driver is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC2G241 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device is organized as two 1-bit line drivers with separate output-enable (1OE, 2OE) inputs. When 1OE is low or 2OE is high, the device passes data from the A inputs to the Y outputs. When 1OE is high or 2OE is low, the outputs are in the high-impedance state.

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To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor, and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

For more information about AUC Little Logic devices, please refer to the TI application report, Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.

Products containing the "SN74AUC2G241" keyword are: SN74AUC2G241DCTR , SN74AUC2G241DCTR , SN74AUC2G241DCUR , SN74AUC2G241DCUR , SN74AUC2G241DCURG4 , SN74AUC2G241YEPR , SN74AUC2G241YZPR , SN74AUC2G241YZPR

• Available in the Texas Instruments NanoFree™ Package
• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• I_off Supports Partial-Power-Down Mode Operation
• Sub-1-V Operable
• Max t_pd of 1.9 ns at 1.8 V
• Low Power Consumption, 10 µA at 1.8 V
• ±8-mA Output Drive at 1.8 V
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

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