SN74AUP1G08 - Low-Power Single 2-Input Positive-AND Gate

Updated : 2020-01-09 14:36:59
Description

This single 2-input positive-AND gate is designed for 0.8-V to 3.6-V VCC operation and performs the Boolean function Y = A • B or Y = A\ + B\ in positive logic.

Products containing the "SN74AUP1G08" keyword are: SN74AUP1G08DBVR , SN74AUP1G08DBVR , SN74AUP1G08DBVRE4 , SN74AUP1G08DBVRE4 , SN74AUP1G08DBVRG4 , SN74AUP1G08DBVT , SN74AUP1G08DBVT , SN74AUP1G08DBVTG4 , SN74AUP1G08DBVTG4 , SN74AUP1G08DCKR , SN74AUP1G08DCKR , SN74AUP1G08DCKR , MAX674 , SN74AUP1G08DCKR , MAX6740XKTID3 , SN74AUP1G08DCKRE4 , SN74AUP1G08DCKRE4 , SN74AUP1G08DCKRG4 , SN74AUP1G08DCKRG4 , SN74AUP1G08DCKT , SN74AUP1G08DCKT , SN74AUP1G08DCKTE4
Features

  • Available in the Ultra Small 0.64 mm2 Package
    (DPW) With 0.5-mm Pitch
  • Low Static-Power Consumption:
    ICC = 0.9 µA Maximum
  • Low Dynamic-Power Consumption:
    Cpd = 4.3 pF Typical at 3.3 V
  • Low Input Capacitance: Ci = 1.5 pF Typical
  • Low Noise: Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back Drive Protection
  • Schmitt-Trigger Action Allows Slow Input
    Transition and Better Switching Noise Immunity at
    the Input (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal
    Operation
  • tpd = 4.3 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)