CD4085B - CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Updated : 2020-01-09 14:38:56
Description

CD4085 contains a pair of AND-OR-INVERT gates, each consisting of two 2-input AND gates driving a 3-input NOR gate. Individual inhibit controls are provided for both A-O-I gates.

The CD4085B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

Products containing the "CD4085B" keyword are: CD4085BE , CD4085BE , CD4085BE. , CD4085BEE4 , CD4085BEG4 , CD4085BEX , CD4085BF , CD4085BF/3 , CD4085BF3A , CD4085BFX , CD4085BFXT , CD4085BM , CD4085BM , CD4085BM96 , CD4085BM96 , CD4085BM96E4 , CD4085BM96E4 , CD4085BM96G4 , CD4085BME4 , CD4085BMG4
Features

  • Medium-speed operation - tPHL = 90 ns; tPLH = 125 ns (typ.) at 10 V
  • Individual inhibit controls
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package-temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

Parametrics
StatusACTIVE
SubFamilyCombination gate
Technology FamilyCD4000
VCC18
Channels2
Inputs per channel2
ICC @ nom voltage0.06
IOL6.8
IOH-6.8
Input typeStandard CMOS
Output typePush-Pull
FeaturesStandard Speed (tpd > 50ns)
Data rate8
RatingCatalog
Operating temperature range-55 to 125
Package GroupPDIP|14
Package size: mm2:W x L (PKG)See datasheet (PDIP)
Approx. price0.13 | 1ku