CD4075B - CMOS Triple 3-Input OR Gate

CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.

The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

Products containing the "CD4075B" keyword are: CD4075B , CD4075BCN , CD4075BD , CD4075BD/3 , CD4075BE , CD4075BE , CD4075BEE4 , CD4075BEE4 , CD4075BEG4 , CD4075BES2064 , CD4075BEX , CD4075BEXV , CD4075BF , CD4075BF/3 , CD4075BF3A , CD4075BF3A. , CD4075BFB , CD4075BFX , CD4075BM , CD4075BM

• Medium-Speed Operation - t_PLH, t_PHL = 60 ns (typ.) at V_DD = 10 V
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Standardized, symmetrical output characteristics
• Noise margin (full package-temperature range):
       1 V at V_DD = 5 V
       2 V at V_DD = 10 V
    2.5 V at V_DD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor