CD4086B - CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to V_SS and ENABLE/EXP to V_DD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required.

The CD4086B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

Products containing the "CD4086B" keyword are: CD4086BE , CD4086BEE4 , CD4086BEX , CD4086BEXV , CD4086BF , CD4086BF3A , CD4086BF3A-TSTDTS , CD4086BFX , CD4086BM , CD4086BM , CD4086BM96 , CD4086BM96 , CD4086BM96E4 , CD4086BM96E4 , CD4086BM96G4 , CD4086BME4 , CD4086BME4 , CD4086BMG4 , CD4086BMJ/883 , CD4086BMT

• Medium-speed operation - t_PHL = 90 ns; t_PLH = 140 ns (typ.) at 10 V
• INHIBIT and ENABLE inputs
• Buffered outputs
• 100% tested for quiescent current at 20 V
• Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
      1 V at V_DD = 5 V
      2 V at V_DD = 10 V
      2.5 V at V_DD = 15 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"