CD4071B - CMOS Quad 2-Input OR Gate

CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.

The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

Products containing the "CD4071B" keyword are: CD4071B , CD4071B/883 , CD4071BC , CD4071BCM , CD4071BCM , ZMM5236 , CD4071BCM,2SB709-R,MT3S0 , CD4071BCMX , CD4071BCMX SOP3.9 , CD4071BCN , CD4071BCN , CD4071BCN(MM5671BN) , CD4071BD , CD4071BD CD4071BP CD4071 , CD4071BD/3 , CD4071BD/CD4017BE , CD4071BDB , CD4071BDC , CD4071BDM , CD4071BDMSR , CD4071BE

• Medium-Speed Operation - t_PLH, t_PHL = 60 ns (typ.) at V_DD = 10 V
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Standardized, symmetrical output characteristics
• Noise margin (full package-temperature range):
       1 V at V_DD = 5 V
       2 V at V_DD = 10 V
    2.5 V at V_DD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor