CD4011B - CMOS Quad 2-Input NAND Gate

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PWR suffix). The CD4011B and CD4023B types also are supplied in 14-lead thin shrink small-outline packages (PW suffix).

Products containing the "CD4011B" keyword are: CD4011B , CD4011BC , CD4011BCJ , CD4011BCM , CD4011BCM,2SA1730S,MSCD1 , CD4011BCMX , CD4011BCMX , CD4011BCMX 0748+ , CD4011BCMX SOP3.9 , CD4011BCMX/SOP , CD4011BCN , CD4011BCN LFP , CD4011BCN/ MM5611BN , CD4011BCNX , CD4011BCN_NL , CD4011BCSJ , CD4011BCSJ , CD4011BCSJX , CD4011BD , CD4011BD CD4011BP CD4011

• Propagation delay time = 60 ns (typ.) at C_L = 50 pF, V_DD = 10 V
• Buffered inputs and outputs
• Standardized symmetrical output characteristics
• Maximum input current of 1 µA at 18 V over-full package temperature range; 100 nA at 18 V and 25°C
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Noise margin (over full package temperature range:
      1 V at V_DD = 5 V
      2 V at V_DD = 10 V
      2.5 at V_DD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of "B" Series CMOS Devices"

Quad 2 Input—CD4011B
Dual 4 Input—CD4012B
Triple 3 Input—CD4023B
Data sheet acquired from Harris Semiconductor.