SN74ABT16543 - 16-Bit Registered Transceivers With 3-State Outputs

The 'ABT16543 16-bit registered transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. The 'ABT16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable ( or) and output-enable ( or ) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable () input must be low to enter data from A or to output data from B. If is low and is low, the A-to-B latches are transparent; a subsequent low-to-high transition of puts the A latches in the storage mode. With and both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the,, and inputs.

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16543 is characterized for operation from -40°C to 85°C.

 

 

 

Products containing the "SN74ABT16543" keyword are: SN74ABT16543DGGR , SN74ABT16543DGGR , SN74ABT16543DGGRG4 , SN74ABT16543DL , SN74ABT16543DL , SN74ABT16543DLG4 , SN74ABT16543DLG4 , SN74ABT16543DLR , SN74ABT16543DLR , SN74ABT16543DLR10 , SN74ABT16543DLRG4

• Members of the Texas Instruments Widebus^TM Family
• State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
• Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
• Flow-Through Architecture Optimizes PCB Layout
• High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
• Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

 

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