CY74FCT2652T - Octal Bus Transceivers and Registers with 3-State Outputs and Series Damping Resistors

The CY74FCT2652T consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. Control (GAB and GBA\) inputs control the transceiver functions. Select-control (SAB and SBA) inputs select either real-time or stored data transfer.

The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during transition between stored and real-time data. A low input level selects real-time data, and a high level selects stored data. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CPAB or CPBA) inputs, regardless of levels at the select- or enable-control inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling GAB and GBA\. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.

On-chip termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2652T can replace the CY74FCT652T to reduce noise in existing designs.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• Function and Pinout Compatible With FCT and F Logic
• 25- Output Series Resistors Reduce Transmission-Line Reflection Noise
• Reduced V_OH (Typically = 3.3 V) Versions of Equivalent FCT Functions
• Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
• I_off Supports Partial-Power-Down Mode Operation
• Matched Rise and Fall Times
• Fully Compatible With TTL Input and Output Logic Levels
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)
• 12-mA Output Sink Current
  15-mA Output Source Current
• Independent Register for A and B Buses
• Multiplexed Real-Time and Stored Data Transfer
• 3-State Outputs