The ADC344x devices are a high-linearity, ultra-low power, quad-channel, 14-bit, 25-MSPSto 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically tosupport demanding, high input frequency signals with large dynamic range requirements. An inputclock divider allows more flexibility for system clock architecture design while the SYSREF inputenables complete system synchronization.
The ADC344x family supports serial low-voltage differential signaling (LVDS) to reducethe number of interface lines, thus allowing for high system integration density. The serial LVDSinterface is two-wire, where each ADC data are serialized and output over two LVDS pairs.Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop(PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serializethe 14-bit output data from each channel. In addition to the serial data streams, the frame and bitclocks are transmitted as LVDS outputs.
Products containing the "ADC3443" keyword are: ADC3443EVM , ADC3443EVM , ADC3443IRTQ25 , ADC3443IRTQ25 , ADC3443IRTQR , ADC3443IRTQR , ADC3443IRTQT , ADC3443IRTQTAll trademarks are the property of their respective owners.
Status | ACTIVE |
SubFamily | High-speed ADCs (>10MSPS) |
Resolution | 14 |
Sample Rate | 80 |
Number of input channels | 4 |
INL | |
SNR | 73.4 |
SFDR | 93 |
Power consumption | 288 |
Interface | Serial LVDS |
Architecture | Pipeline |
Operating temperature range | -40 to 85 |
Rating | Catalog |
Package Group | QFN|56 |
Package size: mm2:W x L (PKG) | [pf]56QFN[/pf]: 64 mm2: 8 x 8 (QFN|56) |
Approx. price | 44.10 | 1ku |
Analog input BW | 540 |