ADC14X250 - 14-Bit, 250-MSPS Analog-to-Digital Converter (ADC)

The ADC14X250 device is a monolithic single-channel high performance analog-to-digitalconverter capable of converting analog input signals into 14-bit digital words with a sampling rateof 250 MSPS. This converter uses a differential pipelined architecture with integrated input bufferto provide excellent dynamic performance and low power consumption across an extended temperaturerange from –40°C to 105°C as measured at the device’s PCB footprint thermal pad.

The integrated input buffer eliminates charge kickback noise coming from the internalswitched capacitor sampling circuits and eases the system-level design of the driving amplifier,anti-aliasing filter, and impedance matching. The buffer can be also be adjusted to correct forphase and amplitude imbalance of the differential input signal path to improve even order harmonicdistortion. An input sampling clock divider provides integer divide ratios to simplify systemclocking. An integrated low-noise voltage reference eases board level design without requiringexternal decoupling capacitors. The output digital data is provided through a JESD204B subclass 1single lane interface from a 32-pin, 5-mm × 5-mm WQFN package. The ADC14X250 operates on 1.2 V, 1.8V and 3.0 V power supplies. A SPI is available to configure the device that is compatible with1.2-V to 3-V logic.

• Resolution: 14-Bit
• Conversion Rate: 250 MSPS
• Performance:
  • Input: 240 MHz, –3 dBFS
    • SNR: 70.1 dBFS
    • Noise Spectral Density: –151.1 dBFS/Hz
    • SFDR: 87 dBFS
    • Non-HD2 and Non-HD3 SPUR: –92 dBFS
  • No Input SNR: 71.1 dBFS
• Power Dissipation: 584 mW
• Performance Rated up to 105°C (at thermal pad)
• JESD204B Subclass 1 Single Lane Serial Data Interface With Lane Rate Up To 5 Gb/s
• Buffered Analog Inputs
• Differential Input Phase and Amplitude Correction
• Input Sampling Clock Divider (Divide-by-1,2,4,8)
• 4-Wire Serial Peripheral Interface (SPI)
• 32-Pin WQFN Package (5×5 mm, 0.5-mm Pitch)

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