SN74VMEH22501 - 8-Bit Universal Bus Transceiver and Two 1-Bit Bus Transceivers with 3-State Outputs

The SN74VMEH22501 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is designed for 3.3-V V_CC operation with 5-V tolerant inputs. The UBT™ transceiver allows transparent, latched, and flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide a feedback path for control and diagnostics monitoring. This device provides a high-speed interface between cards operating at LVTTL logic levels and VME64, VME64x, or VME320⁽¹⁾ backplane topologies.

High-speed backplane operation is a direct result of the improved OEC™ circuitry and high drive that has been designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large capacitive loads and include pseudo-ETL input thresholds (½ V_CC ± 50 mV) for increased noise immunity. These specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in VITA 1.5. With proper design of a 21-slot VME system, a designer can achieve 320-Mbyte transfer rates on linear backplanes and, possibly, 1-Gbyte transfer rates on the VME320 backplane.

All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs.

Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for live-insertion applications using I_off, power-up 3-state, and BIAS V_CC. The I_off circuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS V_CC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.

When V_CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, output-enable (OE and OEBY) inputs should be tied to V_CC through a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this input.

Products containing the "SN74VMEH22501" keyword are: SN74VMEH22501ADGGR , SN74VMEH22501ADGGR , SN74VMEH22501ADGVR , SN74VMEH22501ADGVRG4 , SN74VMEH22501AGQLR , SN74VMEH22501AGQLR , SN74VMEH22501AZQLR , SN74VMEH22501AZQLR , SN74VMEH22501DGG , SN74VMEH22501DGGR , SN74VMEH22501DGGR , SN74VMEH22501DGVR , SN74VMEH22501DGVRG4 , SN74VMEH22501GQLR , SN74VMEH22501ZQLR , SN74VMEH22501ZQLR , SN74VMEH22501ZQLRTI

• Member of the Texas Instruments Widebus™ Family
• UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops
  for Operation in Transparent, Latched, or Clocked Modes
• OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic
  Interference (EMI)
• Compliant With VME64, 2eVME, and 2eSST Protocol
• Bus Transceiver Split LVTTL Port Provides a Feedback Path for Control
  and Diagnostics Monitoring
• I/O Interfaces Are 5-V Tolerant
• B-Port Outputs (–48 mA/64 mA)
• Y and A-Port Outputs (–12 mA/12 mA)
• I_off, Power-Up 3-State, and BIAS V_CC Support Live Insertion
• Bus Hold on 3A-Port Data Inputs
• 26- Equivalent Series Resistor on 3A Ports and Y Outputs
• Flow-Through Architecture Facilitates Printed Circuit Board Layout
• Distributed V_CC and GND Pins Minimize High-Speed Switching Noise
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

MicroStar is a trademark of Texas Instruments.
⁽¹⁾ VME320 is a patented backplane construction by Arizona Digital, Inc.