This 18-bit universal bus driver is designed for 2.3-V to 3.6-V VCC operation.
Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE) input is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
The SN74ALVCF162835 has series damping resistors in the device output structure that reduce switching noise in 128-MB and 256-MB SDRAM modules. Designed with a drive capability of ±18 mA, this device is a midway drive between the SN74ALVC162835 (±12 mA) and SN74ALVC16835 (±24 mA).
The SN74ALVCF162835 is a faster version of the SN74ALVC162835. It is suitable for PC133 applications and, particularly, SDRAM modules clocked at 133 MHz.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Products containing the "SN74ALVCF162835" keyword are: SN74ALVCF162835DL , SN74ALVCF162835DL , SN74ALVCF162835GR , SN74ALVCF162835GR , SN74ALVCF162835GRE4 , SN74ALVCF162835GRG4 , SN74ALVCF162835LR , SN74ALVCF162835VR , SN74ALVCF162835VR , SN74ALVCF162835VRG4Widebus is a trademark of Texas Instruments.
Status | ACTIVE |
SubFamily | Universal bus driver (UBD) |
Technology Family | ALVC |
Rating | Catalog |
Package Group | TSSOP|56 |
Package size: mm2:W x L (PKG) | [pf]56TSSOP[/pf]: 113 mm2: 8.1 x 14 (TSSOP|56) |
Approx. price | 1.06 | 1ku |