SN74ABTH182652A - Scan Test Devices With 18-Bit Transceivers And Registers

The 'ABTH18652A and 'ABTH182652A scan test devices with 18-bit bus transceivers and registers are members of the Texas Instruments SCOPE^TM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed transmission of data directly from the input bus or from the internal registers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE^TM bus transceivers and registers.

Data flow in each direction is controlled by clock (CLKAB and CLKBA), select (SAB and SBA), and output-enable (OEAB and ) inputs. For A-to-B data flow, data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). When OEAB is high, the B outputs are active. When OEAB is low, the B outputs are in the high-impedance state. Control for B-to-A data flow is similar to that for A-to-B data flow, but uses CLKBA, SBA, and inputs. Since the input is active-low, the A outputs are active when is low and are in the high-impedance state when is high. Figure 1 illustrates the four fundamental bus-management functions that are performed with the 'ABTH18652A and 'ABTH182652A.

In the test mode, the normal operation of the SCOPE^TM bus transceivers and registers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A PSA/COUNT instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful.

Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.

The B-port outputs of 'ABTH182652A, which are designed to source or sink up to 12 mA, include 25- series resistors to reduce overshoot and undershoot.

The SN54ABTH18652A and SN54ABTH182652A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABTH18652A and SN74ABTH182652A are characterized for operation from -40°C to 85°C.

• Members of the Texas Instruments SCOPE^TM Family of Testability Products
• Members of the Texas Instruments Widebus^TM Family
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• Include D-Type Flip-Flops and Control Circuitry to Provide Multiplexed Transmission of Stored and Real-Time Data
• Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors
• B-Port Outputs of 'ABTH182652A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
• State-of-the-Art EPIC-IIB^TM BiCMOS Design
• One Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency
• SCOPE^TM Instruction Set
  • IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
  • Parallel-Signature Analysis at Inputs
  • Pseudo-Random Pattern Generation From Outputs
  • Sample Inputs/Toggle Outputs
  • Binary Count From Outputs
  • Device Identification
  • Even-Parity Opcodes
• Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

  SCOPE, Widebus, and EPIC-IIB are trademarks of Texas Instruments Incorporated.