74ACT16374 - 16-Bit D-Type Edge-Triggered Flip-Flops With 3-State Outputs

The SN54ACT16374 and 74ACT16374 are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

An output-enable input (OE) can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state provides the capability to drive bus lines in a bus-organized system without need for interface or pullup components. OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The 74ACT16374 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit board area.

The SN54ACT16374 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16374 is characterized for operation from -40°C to 85°C.

Products containing the "74ACT16374" keyword are: 74ACT16374DL , 74ACT16374DL , 74ACT16374DLG4 , 74ACT16374DLR , 74ACT16374DLR , 74ACT16374DLRG4 , 74ACT16374DLRG4 , 74ACT16374MTD , 74ACT16374MTDX , 74ACT16374SSC , 74ACT16374SSCX , 74ACT16374TTR

• Members of the Texas Instruments Widebus™ Family
• Inputs Are TTL-Voltage Compatible
• 3-State Bus-Driving True Outputs
• Flow-Through Architecture Optimizes PCB Layout
• Distributed Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
• EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings

EPIC and Widebus are trademarks of Texas Instruments Incorporated.