The '73, and 'H73, contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '73, and 'H73, are positive pulse-triggered flip-flops. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.
The 'LS73A contains two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.
The SN5473, SN54H73, and the SN54LS73A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7473, and the SN74LS73A are characterized for operation from 0°C to 70°C.
Products containing the "SN74LS73A" keyword are: SN74LS73AD , SN74LS73AD , SN74LS73ADE4 , SN74LS73ADE4 , SN74LS73ADR , SN74LS73ADR , SN74LS73ADRG4 , SN74LS73ADRG4 , SN74LS73AN , SN74LS73AN , SN74LS73ANE4 , SN74LS73ANE4 , SN74LS73ANG4 , SN74LS73ANS , SN74LS73ANSR
Status | ACTIVE |
SubFamily | J-K flip-flop |
Technology Family | LS |
VCC | 5.25 |
Bits | 2 |
Voltage | 5 |
F @ nom voltage | 35 |
ICC @ nom voltage | 6 |
tpd @ Nom Voltage | 20 |
3-state output | |
Rating | Catalog |
Operating temperature range | 0 to 70 |
Package Group | PDIP|14 |
Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
Approx. price | 0.71 | 1ku |