74AC11074 - Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () input sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The 74AC11074 is characterized for operation from -40°C to 85°C.

 

 

 

Products containing the "74AC11074" keyword are: 74AC11074D , 74AC11074D , 74AC11074DB , 74AC11074DE4 , 74AC11074DE4 , 74AC11074DG4 , 74AC11074DR , 74AC11074DR , 74AC11074DRE4 , 74AC11074DRG4 , 74AC11074DRG4 , 74AC11074N , 74AC11074N , 74AC11074NE4 , 74AC11074NSR , 74AC11074NSRE4 , 74AC11074NSRE4 , 74AC11074NSRG4 , 74AC11074NSRG4 , 74AC11074PWR

• Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
• EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)

 

EPIC is a trademark of Texas Instruments Incorporated.