This positive-edge-triggered D-type flip-flop has a direct clear (CLR)\ input. The CD74AC175 features complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.
Products containing the "CD74AC175" keyword are: CD74AC175E , CD74AC175EX , CD74AC175M , CD74AC175M96 , CD74AC175M96 , CD74AC175M96E4 , CD74AC175M96E4 , CD74AC175M96G4 , CD74AC175M96G4 , CD74AC175ME4 , CD74AC175ME4 , CD74AC175MG4 , CD74AC175NSR , CD74AC175NSR , CD74AC175NSRE4 , CD74AC175NSRG4 , CD74AC175NSRG4Status | ACTIVE |
SubFamily | D-type flip-flop |
Technology Family | AC |
VCC | 5.5 |
Bits | 4 |
Voltage | 1.5^3.3^5 |
F @ nom voltage | 100 |
ICC @ nom voltage | 0.08 |
tpd @ Nom Voltage | 139^15.5^11.1 |
3-state output | No |
Rating | Catalog |
Operating temperature range | -55 to 125 |
Package Group | SOIC|16 |
Package size: mm2:W x L (PKG) | [pf]16SOIC[/pf]: 59 mm2: 6 x 9.9 (SOIC|16) |
Approx. price | 0.26 | 1ku |