SN74LVTH540 - 3.3V ABT Octal Buffers/Drivers With 3-State Outputs

These octal buffers/drivers are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH540 devices are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout.

The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\ or OE2\) input is high, all outputs are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When V_CC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

Products containing the "SN74LVTH540" keyword are: SN74LVTH540DBR , SN74LVTH540DBR , SN74LVTH540DBRG4 , SN74LVTH540DW , SN74LVTH540DW , SN74LVTH540DWR , SN74LVTH540DWR , SN74LVTH540NS , SN74LVTH540NSR , SN74LVTH540NSRG4 , SN74LVTH540NSRG4 , SN74LVTH540PW , SN74LVTH540PW , SN74LVTH540PWG4 , SN74LVTH540PWG4 , SN74LVTH540PWR , SN74LVTH540PWR , SN74LVTH540PWR TSSOP20

• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
• Typical V_OLP (Output Ground Bounce)
     <0.8 V at V_CC = 3.3 V, T_A = 25°C
• Support Unregulated Battery Operation Down to 2.7 V
• I_off and Power-Up 3-State Support Hot Insertion
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 500 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)