SN74LVTH16244A - 3.3-V ABT 16-Bit Buffers/Drivers With 3-State Outputs

The 'LVTH16244A devices are 16-bit buffers and line drivers designed for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical active-low output-enable (OE)  inputs.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When V_CC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

Products containing the "SN74LVTH16244A" keyword are: SN74LVTH16244A , SN74LVTH16244ADGGR , SN74LVTH16244ADGGR , SN74LVTH16244ADGGR /TI , SN74LVTH16244ADGGRG4 , SN74LVTH16244ADGVR , SN74LVTH16244ADL , SN74LVTH16244ADL , SN74LVTH16244ADLG4 , SN74LVTH16244ADLG4 , SN74LVTH16244ADLR , SN74LVTH16244ADLR , SN74LVTH16244ADLR SSOP48 , SN74LVTH16244AGQLR , SN74LVTH16244AGQLR , SN74LVTH16244AGRDR , SN74LVTH16244AGRDR , SN74LVTH16244AZQLR , SN74LVTH16244AZQLR , SN74LVTH16244AZRDR

• Members of the Texas Instruments Widebus Family
• State-of-the-Art Advanced BiCMOS
  Technology (ABT) Design for 3.3-V
  Operation and Low Static-Power
  Dissipation
• Support Mixed-Mode Signal Operation
  (5-V Input and Output Voltages With
  3.3-V V_CC)
• Support Unregulated Battery Operation
  Down to 2.7 V
• Typical V_OLP (Output Ground Bounce)
  <0.8 V at V_CC = 3.3 V, T_A = 25°C
• I_off and Power-Up 3-State Support Hot
  Insertion
• Bus Hold on Data Inputs Eliminates the Need
  for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 500 mA
  Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)