SN74LVC1G34 - Single Buffer Gate

Updated : 2020-01-09 14:33:10
Description

This single buffer gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G34 device performs the Boolean function Y = A in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC Operating range.

The SN74LVC1G34 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

Products containing the "SN74LVC1G34" keyword are: SN74LVC1G34DBVR , SN74LVC1G34DBVR , SN74LVC1G34DBVRE4 , SN74LVC1G34DBVRE4 , SN74LVC1G34DBVRG4 , SN74LVC1G34DBVRG4 , SN74LVC1G34DBVT , SN74LVC1G34DBVT , SN74LVC1G34DBVTE4 , SN74LVC1G34DBVTE4 , SN74LVC1G34DBVTG4 , SN74LVC1G34DBVTG4 , SN74LVC1G34DCKR , SN74LVC1G34DCKR , SN74LVC1G34DCKRE4 , SN74LVC1G34DCKRE4 , SN74LVC1G34DCKRG4 , SN74LVC1G34DCKRG4 , SN74LVC1G34DCKT , SN74LVC1G34DCKT
Features

  • Available in the Ultra Small 0.64-mm2
    Package (DPW) with 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 3.5 ns at 3.3 V
  • Low Power Consumption, 1-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial Power Down
    Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)