The SN74LVC2G125-Q1 is a dual bus buffer gate designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Status | ACTIVE |
SubFamily | Non-Inverting buffer/driver |
Technology Family | LVC |
VCC | 5.5 |
Bits | 2 |
Voltage | 1.8^2.5^3.3^5 |
F @ nom voltage | 150 |
tpd @ Nom Voltage | 9.1^4.8^4.3^3.7 |
ICC @ nom voltage | 0.01 |
IOL | 32 |
IOH | -32 |
Rating | Automotive |
Operating temperature range | -40 to 85 |
Package Group | SM8|8 |
Package size: mm2:W x L (PKG) | [pf]8SM8[/pf]: 12 mm2: 4 x 2.95 (SM8|8) |
Approx. price | 0.16 | 1ku |