This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC125A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
Products containing the "SN74LVC125A" keyword are: SN74LVC125A , SN74LVC125AD , SN74LVC125AD , SN74LVC125ADBR , SN74LVC125ADBR , SN74LVC125ADBRG4 , SN74LVC125ADBRG4 , SN74LVC125ADE4 , SN74LVC125ADE4 , SN74LVC125ADG4 , SN74LVC125ADG4 , SN74LVC125ADR , SN74LVC125ADR , SN74LVC125ADR (PB) , SN74LVC125ADR(LF) , SN74LVC125ADR(P/B) , SN74LVC125ADR(PBFREE) , SN74LVC125ADRE4 , SN74LVC125ADRE4 , SN74LVC125ADRG3All other trademarks are the property of their respective owners
Status | ACTIVE |
SubFamily | Non-Inverting buffer/driver |
Technology Family | LVC |
VCC | 3.6 |
Bits | 4 |
Voltage | 1.8^2.5^2.7^3.3 |
F @ nom voltage | 100 |
tpd @ Nom Voltage | 11.8^5.8^5.3^4.6 |
ICC @ nom voltage | 0.04 |
IOL | 24 |
IOH | -24 |
Rating | Catalog |
Operating temperature range | -40 to 125 |
Package Group | SOIC|14 |
Package size: mm2:W x L (PKG) | [pf]14SO[/pf]: 80 mm2: 7.8 x 10.2 (SO|14) |
Approx. price | 0.08 | 1ku |