The ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Products containing the "SN74ABT125" keyword are: SN74ABT125D , SN74ABT125D , SN74ABT125DBR , SN74ABT125DBR , SN74ABT125DBR AB125 , SN74ABT125DBR SSOP14 , SN74ABT125DBRG4 , SN74ABT125DE4 , SN74ABT125DE4 , SN74ABT125DG4 , SN74ABT125DG4 , SN74ABT125DR , SN74ABT125DR , SN74ABT125DR SOP3.9 , SN74ABT125DRE4 , SN74ABT125DRE4 , SN74ABT125DRG4 , SN74ABT125DRG4 , SN74ABT125N , SN74ABT125NStatus | ACTIVE |
SubFamily | Non-Inverting buffer/driver |
Technology Family | ABT |
VCC | 5.5 |
Bits | 4 |
Voltage | 5 |
F @ nom voltage | 150 |
tpd @ Nom Voltage | 4.9 |
ICC @ nom voltage | 0.25 |
IOL | 64 |
IOH | -32 |
Rating | Catalog |
Operating temperature range | -40 to 85 |
Package Group | PDIP|14 |
Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
Approx. price | 0.23 | 1ku |