The SN74LVC1G99-Q1 is operational from 1.65 V to 5.5 V.
The SN74LVC1G99-Q1 features configurable multiple functions with a 3-state output. The output is disabled when the output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input. The user can choose logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND.
This device functions as an independent inverter, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Status | ACTIVE |
SubFamily | Configurable gate |
Technology Family | LVC |
VCC | 5.5 |
Channels | 1 |
Inputs per channel | 1 |
ICC @ nom voltage | 0.01 |
IOL | 32 |
IOH | -32 |
Input type | Standard CMOS |
Output type | 3-State |
Features | Partial Power Down (Ioff)^Over-Voltage Tolerant Inputs^Output Enable^Very High Speed (tpd 5-10ns) |
Data rate | 100 |
Rating | Automotive |
Operating temperature range | -40 to 125 |
Package Group | VSSOP|8 |
Package size: mm2:W x L (PKG) | [pf]8VSSOP[/pf]: 6 mm2: 3.1 x 2 (VSSOP|8) |
Approx. price | 0.16 | 1ku |