SN74AUP2G32 - Low-Power Dual 2-Input Positive-OR Gate

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

The SN74AUP2G32 performs the Boolean function Y = A + B or Y = A\ • B\ in positive logic.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Products containing the "SN74AUP2G32" keyword are: SN74AUP2G32DCUR , SN74AUP2G32DCUR , SN74AUP2G32DCURG4 , SN74AUP2G32DQER , SN74AUP2G32DQER , SN74AUP2G32RSER , SN74AUP2G32RSER , SN74AUP2G32YFPR , SN74AUP2G32YFPR

• Available in the Texas Instruments NanoStar™ Package
• Low Static-Power Consumption
  (I_CC = 0.9 µA Maximum)
• Low Dynamic-Power Consumption
  (C_pd = 4.3 pF Typ at 3.3 V)
• Low Input Capacitance (C_i = 1.5 pF Typical)
• Low Noise – Overshoot and Undershoot
  <10% of V_CC
• I_off Supports Partial-Power-Down Mode Operation
• Wide Operating V_CC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• t_pd = 4.3 ns Maximum at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Performance Tested Per JESD 22
  • 2000-V Human-Body Model
    (A114-B, Class II)
  • 1000-V Charged-Device Model (C101)

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