These quadruple 2-input positive-OR gates are designed for 2-V to 5.5-V VCC operation.
The SN74LV32A performs the Boolean function Y = A + B or Y = A B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
| Status | ACTIVE |
| SubFamily | OR gate |
| Technology Family | LV-A |
| VCC | 5.5 |
| Channels | 4 |
| Inputs per channel | 2 |
| ICC @ nom voltage | 0.02 |
| IOL | 12 |
| IOH | -12 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Features | Partial Power Down (Ioff)^Over-Voltage Tolerant Inputs^Very High Speed (tpd 5-10ns) |
| Data rate | 70 |
| Rating | Automotive |
| Operating temperature range | -40 to 105 |
| Package Group | TSSOP|14 |
| Package size: mm2:W x L (PKG) | [pf]14TSSOP[/pf]: 32 mm2: 6.4 x 5 (TSSOP|14) |
| Approx. price | 0.14 | 1ku |