CD4019B - CMOS Quad AND/OR Select Gate

CD4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single-input OR gate. Selection is accomplished by control bits K_a and K_b. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.

The CD4019B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

Products containing the "CD4019B" keyword are: CD4019BCJ , CD4019BCM , CD4019BCMX , CD4019BCN , CD4019BD , CD4019BD/3 , CD4019BE , CD4019BE , CD4019BEE4 , CD4019BEE4 , CD4019BEG4 , CD4019BF , CD4019BF/3 , CD4019BF3A , CD4019BF3A CD4019BF , CD4019BFB , CD4019BFX , CD4019BFXT , CD4019BM , CD4019BM

• Medium speed operation……t_PHL = t_PLH = 60 ns (typ.) at C_L = 50 pF, V_DD = 10 V
• Standardized, symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (full package-temperature range) =
          1 V at V_DD = 5 V
          2 V at V_DD = 10 V
       2.5 V at V_DD = 15 V
• Applications:
  • AND-OR select gating
  • Shift-right/shift-left registers
  • True/complement selection
  • AND/OR/Exclusive-OR selection