DLP7000 - DLP® 0.7 XGA 2xLVDS Type-A DMD

The DLP7000 XGA Chipset is part of theDLP^®Discovery™ 4100 platform, which enables highresolution and high performance spatial light modulation. The DLP7000 is the digital micromirrordevice (DMD) fundamental to the 0.7 XGA chipset, and currently supports the fastest pattern ratesin the DLP catalog portfolio. The DLP Discovery 4100 platform also provides the highest level ofindividual micromirror control with the option for random row addressing. Combined with a hermeticpackage, the unique capability and value offered by DLP7000 makes it well suited to support a widevariety of industrial, medical, and advanced display applications.

In addition to the DLP7000 DMD, the 0.7 XGA Chipset includes these components:

Reliable function and operation of the DLP7000 requires that it be used in conjunctionwith the other components of the chipset. A dedicated chipset provides developers easier access tothe DMD as well as high speed, independent micromirror control.

DLP7000 is a digitally controlled micro-electromechanical system (MEMS) spatial lightmodulator (SLM). When coupled to an appropriate optical system, the DLP7000 can be used to modulatethe amplitude, direction, and/or phase of incoming light.

Electrically, the DLP7000 consists of a two-dimensional array of 1-bit CMOS memory cells,organized in a grid of 1024 memory cell columns by 768 memory cell rows. The CMOS memory array isaddressed on a row-by-row basis, over two 16-bit low voltage differential signaling (LVDS) doubledata rate (DDR) buses. Addressing is handled via a serial control bus. The specific CMOS memoryaccess protocol is handled by the DLPC410 digital controller.

• 0.7-Inch Diagonal Micromirror Array
  • 1024 × 768 Array of Aluminum, Micrometer-Sized Mirrors
  • 13.68-µm Micromirror Pitch
  • ±12° Micromirror Tilt Angle (Relative to Flat State)
  • Designed for Corner Illumination
• Designed for Use with Broadband Visible Light (400 to 700 nm):
  • Window Transmission 97% (Single Pass, Through Two Window Surfaces)
  • Micromirror Reflectivity 88%
  • Array Diffraction Efficiency 86%
  • Array Fill Factor 92%
• Two 16-Bit, Low Voltage Differential Signaling (LVDS) Double Data Rate (DDR) Input Data Buses
• Up to 400 MHz Input Data Clock Rate
• 40.64-mm by 31.75-mm by 6.0-mm Package Footprint
• Hermetic Package

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