DLPC910 - DLPC910 Digital Controller for the DLP9000X DMD

Updated : 2020-01-09 14:31:22

The DLPC910 device is required for reliable operation of the DLP9000X and DLP6500 family of DMDs. This device enables one of the highest performing DLP® chipsets.

The DLPC910 provides a high-speed data and control interface for the DMD enabling binary pattern rates of up to 15 kHz with the DLP9000X and 11.5 kHz with the DLP6500. These fast pattern rates set DLP technology apart from other spatial light modulators and offer customers a strategic advantage for equipment needing fast, accurate, and programmable light steering capability. The DLPC910 provides the required mirror clocking pulses and timing information to the DMD. The unique capability and value offered by the DLPC910 device makes it well suited to support a wide variety of lithography, industrial, and advanced display applications.

In DLP-based electronics solutions, image data is 100% digital from the DLPC910 input port to the projected image. The image stays in digital form and is never converted into an analog signal. The DLPC910 processes the digital input image and converts the data into a format needed by the DMD for proper display. The DMD then steers the light to the location determined by the pixel data loaded into the DMD.

For complete electrical and mechanical specifications of the DLPC910, see the Virtex®-5 product specification at www.xilinx.com.

Products containing the "DLPC910" keyword are: DLPC910ZYR , DLPC910ZYR

  • Required for Reliable Operation of the DLP9000X and DLP6500 Family of Digital Micromirror Devices (DMDs)
  • User-Selectable Input Clock Rate
    • 400 MHz and 480 MHz with the DLP9000X
    • 400 MHz with the DLP6500
  • Continuous Streaming Input Data
    • Up to 61 Gigabits per Second with the DLP9000X
    • Up to 24 Gigabits per Second with the DLP6500
  • Enables High-Speed Pattern Rates
    • Up to 15 kHz Binary Patterns per Second with the DLP9000X
    • Up to 11.5 kHz Binary Patterns per Second with the DLP6500
  • 8-Bit Gray Scale Pattern Rates
    • Up to 1.8 kHz with the DLP9000X with Modulated Illumination
    • Up to 1.4 kHz with the DLP6500 with Modulated Illumination
  • 64-Bit 2x LVDS Data Bus Interface
  • Supports Random DMD Row Addressing and Load4 Loading
  • Compatible With a Variety of User-Defined Application Processors or FPGAs
  • Integrated I2C Interface for General Control and Status Queries

SubFamilyHigh speed visible
Illumination wavelength rangeN/A
Micromirror array sizeN/A
Chipset familyDLP6500^DLP9000
Micromirror pitch
Component typeDigital Controller
Number of triggers0 / 0
Micromirror array orientationN/A
Micromirror driver supportIntegrated
Package GroupFCBGA|676
Power consumption, typical3.2
Thermal Dissipation (°C/W)
Approx. price335.23 | 100u