SN74FB2031 - 9-Bit TTL/BTL Address/Data Transceiver

The SN74FB2031 is a 9-bit transceiver designed to translate signals between TTL and backplane transceiver logic (BTL) environments. The device is designed specifically to be compatible with IEEE Std 1194.1-1991.

The B\ port operates at BTL-signal levels. The open-collector B\ ports are specified to sink 100 mA. Two output enables (OEB and OEB\) are provided for the B\ outputs. When OEB is low, OEB\ is high, or V_CC is less than 2.1 V, the B\ port is turned off.

The A port operates at TTL signal levels. The A outputs reflect the inverse of the data at the B\ port when the A-port output enable (OEA) is high. When OEA is low or V_CC is less than 2.1 V, the A outputs are in the high-impedance state.

Pins are allocated for the four-wire IEEE Std 1149.1 (JTAG) test bus, although currently there are no plans to release a JTAG-featured version. TMS and TCK are not connected and TDI is shorted to TDO.

BIAS V_CC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when V_CC is not connected.

BG V_CC and BG GND are the supply inputs for the bias generator.

Products containing the "SN74FB2031" keyword are: SN74FB2031RC , SN74FB2031RC , SN74FB2031RCG3 , SN74FB2031RCR , SN74FB2031RCR , SN74FB2031RCRG3 , SN74FB2031RCRG3

• Compatible With IEEE Std 1194.1-1991 (BTL)
• TTL A Port, Backplane Transceiver Logic (BTL) B\ Port
• Open-Collector B\-Port Outputs Sink 100 mA
• High-Impedance State During Power Up and Power Down
• BIAS V_CC Minimizes Signal Distortion During Live Insertion or Withdrawal
• B\-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage
• TTL-Input Structures Incorporate Active Clamping to Aid in Line Termination