SN74AVCH4T245 - 4-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs

This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V_CCB. V_CCB accepts any supply voltage from 1.2 V to 3.6 V. The SN74AVCH4T245 is optimized to operate with V_CCA/V_CCB set at 1.4 V to 3.6 V. It is operational with V_CCA/V_CCB as low as 1.2 V. This allows for universal low voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVCH4T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess I_CC and I_CCZ.

The SN74AVCH4T245 device control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by V_CCA.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The V_CC isolation feature ensures that if either V_CC input is at GND, then both ports are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.

Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pull-up or pull-down resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry on the powered-up side always stays active.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

• Control Inputs V_IH/V_IL Levels are Referenced to
  V_CCA Voltage
• Fully Configurable Dual-Rail Design Allows Each
  Port to Operate Over the Full 1.2V to 3.6V Power-
  Supply Range
• I/Os Are 4.6V Tolerant
• I_off Supports Partial Power-Down-Mode Operation
• Bus Hold on Data Inputs Eliminates the Need for
  External pull-up/pull-down Resistors
• Max Data Rates
  • 380 Mbps (1.8 V to 3.3 V Translation)
  • 200 Mbps (<1.8 V to 3.3 V Translation)
  • 200 Mbps (Translate to 2.5 V or 1.8 V)
  • 150 Mbps (Translate to 1.5 V)
  • 100 Mbps (Translate to 1.2 V)
• Latch-Up Performance Exceeds 100 mA Per
  JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 8000 V Human Body Model (A114-A)
  • 200 V Machine Model (A115-A)
  • 1000 V Charged-Device Model (C101)