SN74ACT1284 - 7-Bit Bus Interfaces With 3-State Outputs

The ’ACT1284 devices are designed for asynchronous two-way communication between data buses. The control function minimizes external timing requirements.

The devices allow data transmission in either the A-to-B or the B-to-A direction for bits 1, 2, 3, and 4, depending on the logic level at the direction-control (DIR) input. Bits 5, 6, and 7, however, always transmit in the A-to-B direction.

The output drive for each mode is determined by the high-drive (HD) control pin. When HD is high, the high drive is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the drive requirements as specified in the IEEE 1284-I (level-1 type) and the IEEE 1284-II (level-2 type) parallel peripheral-interface specification.

Products containing the "SN74ACT1284" keyword are: SN74ACT1284DBR , SN74ACT1284DBR , SN74ACT1284DBRG4 , SN74ACT1284DW , SN74ACT1284DW , SN74ACT1284DWG4 , SN74ACT1284DWR , SN74ACT1284DWR , SN74ACT1284DWRG4 , SN74ACT1284NSR , SN74ACT1284NSR , SN74ACT1284PW , SN74ACT1284PW , SN74ACT1284PWE4 , SN74ACT1284PWG4 , SN74ACT1284PWR , SN74ACT1284PWR , SN74ACT1284PWRG4

• 4.5-V to 5.5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 20 ns at 5 V
• 3-State Outputs Directly Drive Bus Lines
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
• Designed for the IEEE 1284-I (Level-1 Type) and IEEE 1284-II (Level-2 Type) Electrical Specifications