CD40109B - CMOS Quad Low-to-High Voltage Level Shifter (20V Rating)

CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = V_CC and logical 0 = V_SS to a higher-voltage output signal (E, F, G, H) with logical 1 = V_DD and logical 0 = V_SS.

The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (V_DD) before the application of either the low-voltage supply (V_CC) or the input signals. There are no restrictions on the sequence of application of V_DD, V_CC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between V_SS and at least 0.7 V_CC; V_CC may exceed V_DD, and input signals may exceed V_CC and V_DD. When operated in the mode V_CC > V_DD, the CD40109 will operate as a high-to-low level-shifter.

The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.

The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

Products containing the "CD40109B" keyword are: CD40109BD , CD40109BD/3 , CD40109BDMSR , CD40109BE , CD40109BE , CD40109BEE4 , CD40109BEX , CD40109BF , CD40109BF/3 , CD40109BF3A , CD40109BFX , CD40109BK/3 , CD40109BNSR , CD40109BNSR , CD40109BNSRE4 , CD40109BNSRE4 , CD40109BNSRG4 , CD40109BPW , CD40109BPW , CD40109BPWE4

• Independence of power supply sequence considerations - V_CC can exceed V_DD, input signals can exceed both V_CC and V_DD
• Up and down level-shifting capability
• Three-state outputs with separate enable controls
• Standardized, symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (full package-temperature range):
     = 1 V at V_CC = 5 V, V_DD = 10 V
     = 2 V at V_CC = 10 V, V_DD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
• Applications:
  • High-or-low level-shifting with three-state outputs for unidirectional or bidirectional bussing.
  • Isolation of logic subsystems using separate power supplies from supply sequencing, supply loss and supply regulation considerations

Data sheet acquired from Harris Semiconductor