The CDCVF25081 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks to the input clock signal. The CDCVF25081 operates from a nominal supply voltage of 3.3 V. The device also includes integrated series-damping resistors in the output drivers that make it ideal for driving point-to-point loads.
Two banks of four outputs each provide low-skew, low-jitter copies of CLKIN. All outputs operate at the same frequency. Output duty cycles are adjusted to 50%, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN and the outputs go into a low state. Unlike many products containing PLLs, the CDCVF25081 does not require an external RC network. The loop filter for the PLL is included on-chip, minimizing component count, space, and cost.
Because it is based on a PLL circuitry, the CDCVF25081 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency signal at CLKIN and any following changes to the PLL reference.
The CDCVF25081 is characterized for operation from -40°C to 85°C.
Products containing the "CDCVF25081" keyword are: CDCVF25081D , CDCVF25081D , CDCVF25081DG4 , CDCVF25081DG4 , CDCVF25081DR , CDCVF25081DR , CDCVF25081DRG4 , CDCVF25081DRG4 , CDCVF25081PW , CDCVF25081PW , CDCVF25081PWG4 , CDCVF25081PWG4 , CDCVF25081PWR , CDCVF25081PWR , CDCVF25081PWRG4 , CDCVF25081PWRG4Status | ACTIVE |
SubFamily | Zero delay buffers |
Additive RMS jitter | |
Output frequency | |
Input level | |
Number of outputs | 8 |
Output level | |
VCC | 3.3 |
VCC out | |
Input frequency | |
Operating temperature range | -40 to 85 |
Package Group | SOIC|16 |
Package size: mm2:W x L (PKG) | [pf]16SOIC[/pf]: 59 mm2: 6 x 9.9 (SOIC|16) |
Rating | Catalog |
Approx. price | 1.74 | 1ku |