The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN)\ to nine pairs of differential clock (Y, Y)\ outputs with minimum skew for clock distribution. It is specifically designed for driving 50- transmission lines.
The VREF output can be strapped to the CLKIN\ input for a single-ended CLKIN input.
The CDCVF111 is characterized for operation from 40°C to 85°C.
Products containing the "CDCVF111" keyword are: CDCVF111FN , CDCVF111FN , CDCVF111FNG4 , CDCVF111FNG4 , CDCVF111FNR , CDCVF111FNR , CDCVF111FNRG4 , CDCVF111FNRG4Status | ACTIVE |
SubFamily | Differential |
Additive RMS jitter | N/A |
Output frequency | 650 |
Input level | LVPECL |
Number of outputs | 9 |
Output level | LVPECL |
VCC | 3.3 |
VCC out | 3.3 |
Input frequency | 650 |
Operating temperature range | -40 to 85 |
Package Group | PLCC|28 |
Package size: mm2:W x L (PKG) | [pf]28PLCC[/pf]: 155 mm2: 12.45 x 12.45 (PLCC|28) |
Rating | Catalog |
Approx. price | 9.65 | 1ku |