SN74LVTH2952 - 3.3-V ABT Octal Bus Transceivers And Registers With 3-State Outputs

These octal bus transceivers and registers are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH2952 devices consist of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB\ or CLKENBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses the data on either port.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When V_CC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

Products containing the "SN74LVTH2952" keyword are: SN74LVTH2952DBR , SN74LVTH2952DBRE4 , SN74LVTH2952DBRG4 , SN74LVTH2952DGVR , SN74LVTH2952DGVR , SN74LVTH2952DGVRG4 , SN74LVTH2952DW , SN74LVTH2952DW , SN74LVTH2952DWR , SN74LVTH2952DWRE4 , SN74LVTH2952DWRG4 , SN74LVTH2952DWRG4 , SN74LVTH2952NSR , SN74LVTH2952NSR , SN74LVTH2952NSRE4 , SN74LVTH2952NSRG4 , SN74LVTH2952PW , SN74LVTH2952PW , SN74LVTH2952PWR , SN74LVTH2952PWR

• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
• Support Unregulated Battery Operation Down to 2.7 V
• Typical V_OLP (Output Ground Bounce)
     <0.8 V at V_CC = 3.3 V, T_A = 25°C
• I_off and Power-Up 3-State Support Hot Insertion
• Bus-Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 500 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)