SN74LVTH16652-EP - Enhanced Product 3.3 V Abt 16-Bit Bus Transceivers And Registers With 3-State Outputs

The SN74LVTH16652 is a 16-bit bus transceiver designed for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver.

Output-enable (OEAB and OEBA\) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74LVTH16652.

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last level configuration.

When V_CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to V_CC through a pullup resistor, and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

This device is fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

• Controlled Baseline
  • One Assembly/Test Site, One Fabrication Site
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree
• Member of the Texas Instruments Widebus™ Family
• State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
• Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
• Supports Unregulated Battery Operation Down To 2.7 V
• Typical V_OLP (Output Ground Bounce)
     <0.8 V at V_CC = 3.3 V, T_A = 25°C
• I_off and Power-Up 3-State Support Hot Insertion
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Distributed V_CC and GND Pins Minimize High-Speed Switching Noise
• Flow-Through Architecture Optimizes PCB Layout
• Latch-Up Performance Exceeds 500 mA Per JESD 17
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Thin Shrink Small-Outline (DGG) Package

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
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