This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\) and clock-enable (CLKENBA\) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL\) input.
Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKENBA\ input is low. The B-to-A data transfer is synchronized with CLK.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
Products containing the "SN74ALVCH16524" keyword are: SN74ALVCH16524DGGR , SN74ALVCH16524DL , SN74ALVCH16524DL , SN74ALVCH16524DLR , SN74ALVCH16524DLRWidebus, UBT are trademarks of Texas Instruments.
Status | ACTIVE |
SubFamily | Registered transceiver |
Technology Family | ALVC |
VCC | 3.6 |
Bits | 18 |
Voltage | 1.8^2.5^2.7^3.3 |
F @ nom voltage | 150 |
tpd @ Nom Voltage | 3.9^3.8^3.2 |
IOL | 24 |
Rating | Catalog |
Operating temperature range | -40 to 85 |
Package Group | SSOP|56 |
Package size: mm2:W x L (PKG) | [pf]56SSOP[/pf]: 191 mm2: 10.35 x 18.42 (SSOP|56) |
Approx. price | 5.18 | 1ku |
Schmitt Trigger | No |