These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
When the output-enable (OE)\ is low, the device passes noninverted data from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. A high on (OE)\ disables the device so that the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, (OE)\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
| Status | ACTIVE |
| SubFamily | Standard transceiver |
| Technology Family | ACT |
| VCC | 5.5 |
| Bits | 8 |
| Voltage | 5 |
| F @ nom voltage | 90 |
| tpd @ Nom Voltage | 9 |
| IOL | 24 |
| Rating | Space |
| Operating temperature range | -55 to 125 |
| Package Group | CDIP|20 |
| Package size: mm2:W x L (PKG) | See datasheet (CDIP) |
| Approx. price | |
| Schmitt Trigger | No |