CD54HC646 - High Speed CMOS Logic Octal Inverting Bus Transceiver with 3-State Outputs

The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices.

Output-enable (OE\) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either or both registers.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE\ is active (low). In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.

When an output function is disabled, the input function still is enabled and can be used to store data. Only one of the two buses, A or B, can be driven at a time.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Products containing the "CD54HC646" keyword are: CD54HC646F , CD54HC646F3A , CD54HC646F3A 5962-8688 , CD54HC646F3A(5962-868850

• 2-V to 6-V V_CC Operation (CD54HC646)
• 4.5-V to 5.5-V V_CC Operation (CD74HCT646)
• Wide Operating Temperature Range of –55°C to 125°C
• Balanced Propagation Delays and Transition Times
• Standard Outputs Drive Up To 15 LS-TTL Loads
• Significant Power Reduction Compared to LS-TTL Logic ICs
• Inputs Are TTL-Voltage Compatible (CD74HCT646)
• Independent Registers for A and B Buses
• Multiplexed Real-Time and Stored Data
• True Data Paths